A 3D conceptual visualization model that bridges Operating Systems and Computer Architecture — showing not just what each component does, but when and why it becomes active during real program execution.
Traditional CS education teaches OS and COA as separate subjects. Students learn cache mapping, paging, and instruction cycles in isolation — but rarely see how they connect during actual program execution. This model fixes that.
A single 3D spatial environment unifies the OS and COA planes — from user input and kernel intervention down to DMA transfers and CPU instruction cycles.
Physical distance and object shape encode technical constraints. Cache sits close to the Control Unit. HDD sits far. The spatial layout itself teaches the latency hierarchy.
Track the same data block as it moves across system planes — eliminating the "black box" disconnect common in traditional textbook learning.
The framework naturally extends to context switching, deadlock scenarios, scheduling algorithms, ILP, and more — it's a platform, not a single-topic tool.
A cross-layer 3D environment built in Unity — spanning CPU internals, OS process states, memory hierarchy, DMA paths, file systems, and interrupt handling in a single unified space.
CPU Components — CU, ALU, Cache, Registers, TLB with bus architecture
DMA Controller, Storage Controller and cross-layer memory paths
OS Process States — New, Ready, Running, Waiting with PCB Manager
Three video modules walk through the model from structural anatomy to end-to-end causal flow to deep-dive instruction cycles.
If a module doesn't load immediately, wait a moment — Google Drive previews can take a few seconds on first load.
⚠ These walkthroughs were recorded as live narrations — minor technical inaccuracies may exist in the verbal explanation. The spatial model itself is the primary reference.
A public writing series explaining CPU execution, memory hierarchy, and OS concepts through everyday Indian analogies. No jargon. No definitions without context.
Part 01
Instruction format, opcode, addressing modes — explained through a local restaurant token system.
Read article →Part 02
Control Bus, Address Bus, Data Bus — and the complete Fetch → Decode → Execute conversation.
Read article →Part 03
How the clock synchronizes billions of operations per second — and what GHz really means.
Read article →Part 04
How parallel pipeline stages handle multiple instructions simultaneously in one clock tick.
Read article →Part 05
AND, OR, NOT, K-maps, adders — the recipe the ALU follows every time it cooks a result.
Read article →Part 06
TLB, Cache, RAM, SSD/HDD — why proximity to the CPU determines access speed.
Read article →The model is evaluated using a DBR framework with three research questions around cross-layer system literacy, visual design choices, and cognitive load reduction.
Design rationale, abstraction choices, and spatial layout decisions behind the model.
Download PDF →DBR methodology, research questions, experimental intervention modules, and data collection plan.
Download PDF →This is an early-stage prototype built in Unity — a standalone executable for Windows. Compatibility on other systems is not guaranteed. Available on request for research and educational purposes.
Request Access →This project sits at the intersection of computer science education, spatial cognition, and learning design. If any of that overlaps with your work, I'd genuinely love to connect.
If you're exploring how students learn computer architecture, OS concepts, or systems thinking — and want to experiment with spatial or visual models — let's talk.
Interested in how interface design, 3D environments, or interactive tools affect learning outcomes in technical domains? There's a lot of unexplored space here.
If your work touches on cognitive load theory, instructional design, or DBR methodology — especially in STEM — this project might be worth a conversation.
If you build interactive simulations or educational tools in Unity and want to collaborate on extending this model further — animations, interactivity, new modules — reach out.